(tb_y) behaves like a asynchronous flip-flop and block 4. are clearly different, as can be seen in this waveform from the above simulation:īlock 3. It's not even that the coding is ambiguous, always blocks 3. To me this behavior is not correct, as I specifically said I want a flip-flop (with edge triggering). always block will also be synthesized into a latch, which is not the intended behavior and these blocks are not equivalent! The 3. First two always blocks will synthesize to a latch (in Quartus 14), which is OK, as they are equivalent, because of a constant. On the other hand, if on the right side of the assignment there was a VARIABLE, the synthesis would have to infer a flip-flop, because it would matter whether the input is sampled on an edge (flip-flop) or during input latching is enabled (latch), meaning the two logic elements are NOT EQUIVALENT. So the synthesis tool chooses the element that takes less resources, i.e. When this is the case the behavior of a latch and a flip-flop are EQUIVALENT, because it does not matter whether it catches the input value on a signal edge (flip-flop) or while input latching is enabled (latch) as the input does not change.
The reason why this synthesizes to a latch, instead of a flip-flop is because on the right side of the assignment is a CONSTANT. I will share here what I found out so far.
This question comes from the selected best answer from this stackoverflow question: In this case when a negative edge of reset is triggered a gets 0, else it keeps former value. Shouldn't the fact that the always block is sensitive to a signal edge be enough to infer a flip-flop. Could someone explain to me why a latch would be inferred instead of a flip-flop? always_ff (posedge clk, negedge rst)
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